Commit Graph

20 Commits

Author SHA1 Message Date
Jesse Brault
ed6f15a8a9 Making semantic analysis more flexible so we can have a repl again soon. 2026-07-10 22:15:51 -05:00
Jesse Brault
f15ff43df8 Fix test for overlapping register assignments when k=2. 2026-07-03 15:29:33 -05:00
Jesse Brault
a568144ccc Fix pass-through configuration of register count. 2026-07-03 14:58:19 -05:00
Jesse Brault
46ced3980a Some e2e tests passing again. Yay! 2026-06-26 18:22:56 -05:00
Jesse Brault
01df9a708f Complete sketch of interface between dmc-lib compile functions and other modules. 2026-06-25 14:49:32 -05:00
Jesse Brault
737d7b4232 Much work from semantic analysis to lowering to ir/register alloc to assembly. WIP. 2026-06-19 17:07:11 -05:00
Jesse Brault
f9373a687f Refactor to use IrBinaryOperation. 2026-03-15 12:56:22 -05:00
Jesse Brault
f7e8cef380 Yay! Class lookup and allocation e2e. 2026-03-13 20:21:49 -05:00
Jesse Brault
5be778ba80 Fix some ir-related things with fields. 2026-03-13 16:20:08 -05:00
Jesse Brault
8759c3be27 Lots of work e2e for reading/setting fields. 2026-03-13 09:16:41 -05:00
Jesse Brault
320cdcf805 Compiling fields getters/setters. 2026-03-12 21:52:52 -05:00
Jesse Brault
efecd6b9c8 Complete negation operator. 2026-03-11 19:54:47 -05:00
Jesse Brault
ebca87ddb9 A lot of work just to do subtraction. 2026-03-09 19:22:35 -05:00
Jesse Brault
12c4d0eb83 End-to-end with register allocation. 2026-03-08 01:27:09 -06:00
Jesse Brault
4479fcb1ba Refactor register allocation code to separate module. 2026-03-07 17:53:34 -06:00
Jesse Brault
272d288213 Implement block/statement interference graph algorithm. 2026-03-05 20:41:25 -06:00
Jesse Brault
15089a15d2 Re-introduce ir with goal of doing register allocation. 2026-03-05 12:41:05 -06:00
Jesse Brault
8c1d56dc1a Remove ir structs and fix misc. warnings. 2026-03-02 20:15:36 -06:00
Jesse Brault
6b855b8ebb Work on asm. 2026-02-27 21:33:28 -06:00
Jesse Brault
aefac57b9d Starting work on IR. 2026-02-27 16:26:56 -06:00